Staff Verification Engineer

Location: San Jose, California, US

Company: Advanced Micro Devices

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What you do at AMD changes everything 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

This is an exciting opportunity in IP Verification to work in a growing organization in Xilinx DataCenter Business Group . The candidate will have opportunity to work and develop on state-of-art UVM based verification environment on highly-configurable IPs designed towards datacenter performance and acceleration needs. This job will entail 

  • Verifying RTL implementation for complex digital blocks to ensure high quality
  • Developing verification strategies for new features, plan volume validation and coverage strategies
  • Writing testplan, developing testbenches, coding test/sequences and checker to support IP level verification in constrained-random and/or directed verification environments using System Verilog & UVM
  • Working with designers to do coverage analysis and take necessary actions to meet coverage goals
  • Integrate VIPs as needed
  • Closely work with design teams to drive feature enablement
  • Mentor junior engineers on the team



  • BS in EE/CE &  10+ years of experience, or an MS in EE/CE & 7+ years of experience
  • Knowledge of bus protocols like AXI/AHB.
  • PCIe, DMA and/or general CPU architecture knowledge preferred
  • Grounds-up development experience with implementation of UVM/OVM and/or Verilog, System Verilog test benches and/or BFMs is required
  • Strong understanding of simulation tools and knowledge of scripting languages like Perl, tcl or cshell
  • Highly motivated, Self-starter individual with ability to work in a fast-paced team environment


Requisition Number: 155581 
Country: United States State: California City: San Jose 
Job Function: Design

Benefits offered are described here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

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