Analog Mixed-Signal Design Engineer

Location: Santa Clara, California, US

Company: Advanced Micro Devices

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What you do at AMD changes everything 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

Analog Mixed-Signal Design Engineer


The Role

AMD’s Low Power Advanced Development team is seeking talented, self-motivated individuals to help develop low power innovations that enable industry-leading power efficient computing and graphics products. We have openings for R&D engineers to serve as key contributors in small project teams working on low power advanced development projects. 


The Person

A candidate seeking challenging projects in low power design using the latest modern semiconductor technologies, who is eager to learn and collaborate in a Team oriented environment.


Key Responsibilities

  • Working on low power management system design for CPU and GPU applications, custom mixed-signal circuits and logic design in advanced CMOS technologies using custom and semi-custom physical design flows
  • Design, simulate, and verify analog mixed-signal circuits including system level
  • Design mixed-signal architectures for optimum power/speed/area efficiency
  • Closely work with SOC system architects to define mixed-signal design specifications
  • Closely work with Platform architects and Packaging team for Power Integrity and Power Distribution Network analysis in mixed-signal design applications
  • Closely work with and supervise layout/mask designers by providing annotated schematics, floor plans, layout, reliability and manufacturability design guidelines
  • Experience in back-end design verification tools and flows including debugging LVS and DRC issues in collaboration with the layout team
  • Work in collaboration with Physical Design Engineers on mixed-signal design chip level planning and integration
  • Create or in collaboration with other team members design reviews, technical reports, and other documentation required for meeting the design quality and for the tapeout signoff


Preferred Experience

  • Requires strong understanding of analog/mixed signal design concepts, CMOS processes, Package architecture and Chip integration on PCB
  • Knowledge of basic analog blocks: Linear and Switching voltage regulators, DAC, ADC, comparators, oscillators, high speed clock circuits
  • Strong knowledge in Matlab, Verilog-A, Verilog and SystemVerilog
  • Cadence's custom IC design environment with special emphasis on Virtuoso schematic/layout design entry tools
  • Analog/mixed signal circuit simulators, specifically Hspice, Spectre, SpectreRF
  • Good experience in Synopsys based mixed-signal co-simulation flow
  • Scripting: C, python, perl, csh. Experience with TCL is a plus
  • Knowledge in the digital design flows
  • Strong communication skills, teamwork experience and a quick learner in a fast-moving environment


Academic Credentials:  Master's degree in Electrical Engineering (PhD desired)

Location:  Santa Clara, CA



Requisition Number: 133947 
Country: United States State: California City: Santa Clara 
Job Function: Design


AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

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