GPU DFT Design Architect

Location: Santa Clara, California, US

Company: Advanced Micro Devices

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What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

GPU DFT Design Architect

 

Our Graphics team is looking for an experienced DFT design architect professional to drive DFT feature definition and implementation for our next gen Graphics processors.

 

THE ROLE:

  • Drive and implement Design for Test architecture features and methods for high end Graphics IP design
  • Coordinate test and quality requirements across SoC and Product teams
  • Integrate scan control and test compression logic construction to achieve synthesis and physical design requirements
  • Drive DFT optimizations to meet design Power/Performance and Area targets
  • Participate in DRC, test generation and test pattern validation to achieve high test fault coverage targets
  • Construct and validate test vectors across multiple fault models and levels of design hierarchy
  • Drive pre and post silicon structural test debug across design, SoC and product teams
  • Interact with a multi-discipline Geo collocated team

 

THE PERSON:

  • Proven project leader with effective ability to manage simultaneous design development activities and challenges.
  • Proven ability to coordinate deployment of sophisticated features across geo-distributed locations with varied project schedules.
  • Strong organization, problem solving, and analytical skills are a must
  • Goal oriented, self-starter, able to independently drive tasks to completion and work collaboratively across teams.
  • Strong interpersonal skills, including verbal and written communication

  

PREFERRED EXPERIENCE:

  • 7+ years of ASIC/Custom design and testability experience
  • Strong background and experience with Scan design, System and Test Clock architecture, ATPG methodology and commercial EDA tools, including:
  • Scan planning, insertion
  • Compression logic generation
  • Test constraints
  • Test and pattern generation and validation w/wo timing annotation
  • Fault simulation
  • Strong understanding of test models: Stuck At, Transition, Cell Aware, Bridging, etc.
  • Fault analysis and diagnostic capabilities.
  • Solid understanding of scripting, Linux/Unix environment
  • Basic knowledge of logical and physical design (PD) processes
  • Strong organization, problem solving, and analytical skills are must
  • Results oriented, self-starter able to independently drive tasks to completion
  • Strong verbal and written communication skills 

 

#LI-EM1


Requisition Number: 149121 
Country: United States State: California City: Santa Clara 
Job Function: Design
  

Benefits offered are described here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

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