Design Verification Engineer - 75404

Location: Santa Clara, California, US

Company: Advanced Micro Devices

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What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

Position Overview:

  • Candidate will work closely with verification and design engineering community to verify the functional DFT architecture in the Graphics Core
  • Candidate will be responsible for defining and executing verification test plans consisting of directed and random based test sets. Simulate tests to expose specification discrepancies. Evaluate and drive functional and coverage quality. Participate in silicon debug. Experience with hardware modeling, assertions and UVM methods are valuable assets  
  • Candidate expected to participate in development of verification infrastructure to meet the increasingly complex design needs within aggressive and market-driven schedules.

 

Responsibilities include:

  • Review and understand DFT architecture and functionality across the Graphics design
  • Define Design Verification requirements and test implementation specifics in verification plan
  • Construct SystemVerilog and/or C/C++ models and test sequence libraries for simulation
  • Build test bench components including agents, monitors, scoreboards for DUT
  • Compose tests, assertions, checkers, validation vectors and coverage bins to ensure verification completeness
  • Debug regression test failures to expose specification and implementation issues

 

Education and Experience requirements:

  • Min Bachelor of Science Degree in Electrical Engineering, Computer Science or Computer Engineering
  • Strong background in C/C++ and Object Oriented programming
  • Experience with Verilog and/or System Verilog
  • Experience with EDA simulation tools including Synopsys VCS, Cadence NCSIM, Verdi
  • Experience working with UVM, OVM or equivalent
  • Experience with formal verification techniques and industry tools
  • Experience with scripting languages including Tcl/Perl/Ruby/Python
  • Working knowledge of Unix/Linux OS and debug tools
  • Strong analytical skills and attention to detail
  • Excellent written and verbal communication
  • Strong interpersonal skills and proven leadership



Requisition Number: 75404 
Country: United States State: California City: Santa Clara 
Job Function: [[customString7]] 

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

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