Digital Design Engineer- PHY RTL

Location: Santa Clara, California, US

Company: Advanced Micro Devices

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What you do at AMD changes everything 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.


We are searching for an experienced RTL engineer to join the GDDR PHY design team.  This is an exciting opportunity to be a member of the Memory IO design team responsible for defining, specifying, and implementing RTL for the next generation of high-speed GDDR PAM4 and inter-chip IO IP for AMD’s graphics and semi-custom products.



  • Excellent analytical and problem-solving skills along with attention to details
  • Must be a self-starter, able to drive tasks independently and efficiently to completion
    Strong/effective communication skills
  • Enthusiastic team-first mentality



  • Analyze complex digital design problems and propose solutions
  • Develop Verilog RTL and Bus Functional Models
  • Drive/develop ASIC design flows and scripts
  • Create microarchitecture specifications
  • Work with Design Verification team to ensure functional correctness
  • Work with Physical Design team to ensure proper implementation of the design
  • Recommend improvements, optimization and power saving enhancements
    Support silicon bring-up and diagnostics



  • Proven experience in digital design from specification to successful silicon
  • Experience in high-speed interfaces such as DDR, GDDR, HBM, and/or high speed SERDES
  • Experience in designs with multiple power domains
  • Experience in industry standard ASIC CAD tools for simulation, synthesis, STA, CDC, power estimation, etc.
  • Experience in advanced semiconductor technologies, preferably FinFET
  • Progressive experience in RTL Design



Relevant academic background (Master’s degree preferred)



Santa Clara, California





Requisition Number: 166125 
Country: United States State: California City: Santa Clara 
Job Function: Design

Benefits offered are described here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

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