Fellow Silicon Design Engineer - 124741

Location: Santa Clara, California, US

Company: Advanced Micro Devices

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What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

Fellow Design Engineer DFT Architecture and RTL

THE ROLE:

AMD is seeking a Processor DFT Architect and subject matter expert to design and develop custom DFT (Design-For-Test) microarchitecture for our next-generation IPs and processors.  Our candidate is experienced in the microprocessor development process, resolution of critical problems, and has a consistent track record of delivering timely and high-quality products. Cutting edge experience in DFT architecture and design, utilizing the latest process technologies, is required.  Our candidate demonstrates a deep understanding of unique silicon reliability and quality requirements to bring mission critical products to market.

KEY RESPONSIBILITIES:

•             Conceptualize and drive the definition of Design-For-Test Microarchitecture for our next-generation high-performance CPU cores and related IP; meet the highest quality standards of cloud and embedded computing. 

•             Collaborate with DFT stakeholders – ATPG engineers, SOC and other DFT IP experts, Product & Platform Engineering, Processor Architects and process technology experts – to define DFT solutions that ensure the highest levels of silicon quality and reliability.  Overcome challenges that intersect DFT technology and product development.

•             Implementation level specification, microarchitecture design and RTL implementation of custom Design for Test (DFT) solutions. 

•             Collaborate with design verification to validate and ensure production level deployment of features - enabling testability, diagnostics, and high quality. 

•             Collaborate with physical design engineers to achieve high frequency and low power; comprehending challenges of the latest cutting-edge fabrication technologies.

•             Develop technical strategies for DFT.  Demonstrate subject matter expertise.  Actively participate in the external DFT community.

Required experience:

•             Breadth and depth of experience in DFT design, methodology and the latest trends in high-performance microprocessor designs.

•             Evangelize DFT solutions and methodologies, technical leadership and mentoring of senior staff.

•             Experience must include Verilog RTL development with industry tools in a CPU, GPU, or similarly complex semiconductor product. 

Demonstrates expertise in the following:

•             Design-for-test microarchitecture, including scan test, memory built-in self test (MBIST), logic built-in self test (LBIST), and test access with JTAG and IEEE1500 standard logic.

•             Register transfer language (RTL) coding for high-speed designs.

•             Logic design or custom circuit design.

•             Exposure to design verification methods.

•             Experience with physical design, synthesis, place and route, static timing analysis, and power closure.

•             Problem-solving and debugging skills.

•             Excellent communication and technical documentation skills.

Other experience that add value:

•             Experience with clocking, reset, power-up sequences, and power management logic.

•             Experience with design for debug (DFD) and design for manufacturability (DFM).

•             Comfort with scripting such as Python, Ruby, Perl, Shell or TCL

•             Patents and Publications on DFT.

Academic credentials and experience:

•             MS or PhD in EE/CE/CS and 15+ years of relevant work experience

LOCATION:

•             Santa Clara, CA USA

      • AMD is a government contractor and subcontractor. As required by Executive Order, our US employees are required to be fully vaccinated against COVID-19 regardless of the employee’s work location or work arrangement (e.g., telework, remote work, etc.), subject to such exceptions as required by law. If selected, you will be required to be vaccinated against COVID-19 and submit documentation of proof of vaccination by January 4, 2022. AMD will provide additional information regarding what information or documentation will be needed and how you can request an exception from this requirement if you have a need for a religious and/or medical accommodation.


Requisition Number: 124741 
Country: United States State: California City: Santa Clara 
Job Function: Design
  

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

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