Fellow - Memory and interconnect system architect

Location: Santa Clara, California, US

Company: Advanced Micro Devices

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What you do at AMD changes everything 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

Fellow - Memory and interconnect system architect


The Role:

Hardware architect leading a team of architects for various sub-system IPs in graphics and machine intelligence SoCs. This includes the memory sub-system, interconnect fabrics/hubs as well as supporting IP such as DMA engines and interrupt handlers. A good understanding of graphics, multi-media, machine intelligence engine behavior is required. Strong system knowledge is required which ranges from high-speed signaling (memory interfaces) to fabric/hub topologies to capabilities such as coherency/QoS/Virtualization.


This is a leadership position to collaborate with customers, vendors, system (SoC, SW) architects to define sub-system roadmaps and influence product capabilities and SoC/System architectures.  A strong HW background is required to be able to drive innovations for continuous improvements in performance, power, area, quality and time-to-market for a multi-national development team. A strong system knowledge is required to be able to drive platform debug for solving complex cross-functional issues both at the hardware signaling level as well as SW/FW related issues.


The Person:

This is a high visibility role where strong communication skills are essential both for customer facing interactions as well as internally focused engagement which can span from executive level presentations to architecture specifications. An end-to-end ownership mindset is required to continuously think about solving complex problems for the sub-system as well as the overall product. A willingness to collaborate and solve problems at all stages of the hardware development cycle and utilize your technical depth and breadth of knowledge. A willingness to mentor key members of the technical community and drive team growth.


Key Responsibilities:

  • Drive and own the sub-system IP roadmap and specifications.
  • Memory Vendor/JEDEC engagement to define new standards (eg. GDDR/HBM)
  • Grow a team of architects and capabilities towards delivering best-in-class products
  • Drive initiatives for continues improvement in quality as well as time to market.


Preferred Experience:

  • Memory controller and architecture experience related to memory technologies (GDDR, HBM, DDR, LPDDR)
  • Knowledge of architectures and micro-architectures towards improving memory efficiencies across diverse workloads
  • Knowledge of PHY and platform towards solving complex issues such as link-training, di/dt
  • Memory/IO sub-system architecture experience with working with long haul fabrics and aggregation hubs
  • Knowledge of various interconnect solutions/protocols such as CCI, NIC, AXI
  • Knowledge of quality of service architectures for support both real time and non-real time traffic
  • Knowledge of coherency architectures and challenges
  • Skilled at driving debug experiments for platform debug towards root-cause analysis as well as work-around solutions
  • Experience with various flows for pre-silicon and post-silicon development


Academic Credentials:

  • BS / MS / Ph.D in Electrical/Electronic/Computer Engineering or Computer Science is Preferred



Santa Clara

Requisition Number: 147961 
Country: United States State: California City: Santa Clara 
Job Function: Design

Benefits offered are described here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

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