Fellow Silicon Design Engineer

Location: Santa Clara, California, US

Company: Advanced Micro Devices

Apply now

Apply for Job

What you do at AMD changes everything 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.





We are looking for a Fellow-level Engineer to join our Graphics Core HardIP team to develop world-class products around discrete, console and mobile GPUs.  In this role you will be engaged with Graphics architects, micro architecture, RTL, CAD/Methodology, and internal stakeholders to define end to end Power Optimization Methodology, PVT Corners, timing methodology that require technically analyzing, defining usage cases, and mapping across a broad spectrum of technologies to ensure a well-defined methodology to achieve PPA uplift across a spectrum of GPU products. In this role you will provide a cohesive technical vision of the required PPA improvement methodology.



You will possess very strong problem-solving skills and bring broad experience in methodology, with a strong, self-motivated work ethic.



  • Define and drive PPA uplift methodologies for GPU products
  • Develop and deploy end to end power optimization methodology for Physical Design Implementation
  • Define PVT corners, device frequency scaling, frequency targets for next generation GPUs in leading foundry technology nodes
  • Deep knowledge of micro architecture, power optimization methodologies, Synthesis, Place and Route, Top level Clocking structure and Timing closure
  • Proven track record of tapeout experience with leading technology nodes like 10nm, 7nm and 5nm
  • Excellent communication skills and strong collaboration across multiple business units



  • Deep experience in physical design and methodology preferred.
  • Experience working seamlessly across engineering disciplines and geographies to deliver excellent results.



  • Engineering degree in Electrical Engineering, Computer Engineering, or Computer Science with extensive experience.  



Santa Clara, CA


Requisition Number: 168603 
Country: United States State: California City: Santa Clara 
Job Function: Design

Benefits offered are described here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

Apply now

Apply for Job

Share this Job