Lead RTL Design Engineering (IO) - 94322

Location: Santa Clara, California, US

Company: Advanced Micro Devices

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What you do at AMD changes everything 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

Lead RTL Design Engineering (IO)

The role:

We are searching for a Lead RTL Engineer to join the GDDR PHY design team. This is an excellent opportunity to be a member of the Memory IO design team responsible for defining, specifying, and implementing RTL for next generation high-speed GDDR and inter-chip IO IP for AMD’s graphics and semi-custom products.


The person:

We are seeking a candidate that will possess the following skills:

  • Excellent analytical and problem-solving skills along with attention to details
  • Must be a self-starter, able to drive tasks independently and efficiently to completion
  • Strong/effective communication and leadership skills
  • Hardworking team-first mentality
  • Ability to provide mentorship and guidance to junior engineers


Key responsibilities:

  • Lead a group of RTL designers for memory I/O
  • Micro-architecture of analog and digital blocks for memory IO, and firmware partitioning
  • Analyze sophisticated digital design problems and propose solutions, including RTL coding
  • Definition and optimization of training hardware and algorithms including optimization in silicon. Supervision of firmware engineers
  • Work with internal customers to define functional boundaries and specs
  • Work with Design Verification team to ensure functional correctness
  • Work with Physical Design team to ensure accurate implementation of the design
  • Drive/develop ASIC design flow and script improvements
  • Support silicon bring-up and diagnostics


Preferred experience:

  • Confirmed experience in IO/digital design from specification to successful silicon
  • Experience in high speed interfaces such as DDR, GDDR, HBM, and/or high speed SERDES
  • Experience in designs with multiple power and clock domains
  • Strong understanding of digital and analog/mixed-signal electronics.
  • Experience with low level, physical phenomena-oriented logic design is an asset (dealing with IO, clocking, voltage control, etc.)
  • Experience in industry standard ASIC CAD tools for simulation, synthesis, STA, CDC, power estimation, etc.
  • Laboratory experience, including the use of equipment: oscilloscopes, logic analyzers, etc.


Academic credentials:

  • Relevant academic background (Master’s degree preferred)



Santa Clara, California


AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers and will consider all applicants without regard to race, marital status, sex, age, color, religion, national origin, veteran status, disability or any other characteristic protected by law. EOE/MFDV


Requisition Number: 94322 
Country: United States State: California City: Santa Clara 
Job Function: Design


AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

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