ASIC Physical Design Engineer-110183

Location: Santa Clara, California, US

Company: Advanced Micro Devices

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What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

ASIC Physical  Design Engineer

KEY RESPONSIBILITIES:

1. Technical lead of five to eight senior level engineers

2. Tasks to include RTL Synthesis, Placement, Clock tree synthesis, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, IR drop analysis, Physical Verification and Sign Off

3. Identify complex technical problems, break them down, summarize multiple possible solutions, and lead the team in the right direction

4. Drive and hands-on flow development and scripting

5. Technical and schedule discussion with multi-site engineers and managers

 

REQUIREMENTS:

1. Over 6 years experience with MSEE or MSCE in ASIC Physical Design from RTL to GDSII

2. Excellent analytical and problem solving skills along with attention to details

3. Strong RTL analysis skills including Verilog, Timing Analysis and library understanding

4. Hands on experience in taping out 7nm, 10nm, 16nm, 28nm, 32nm, and/or 40nm SOCs

5. Working experience on CAD tools from Synopsys, Cadence and Mentor Graphics

6. Strong communication, Time Management, and Presentation Skills

7. Must be a self-starter, and be able to independently and efficiently drive tasks to completion

8. Ability to provide mentorship and guidance to junior and senior engineers, and be an effective team player

 

BSEE  + 3 years experince  MSEE  desired

 

#LI-JC2



Requisition Number: 110183 
Country: United States State: California City: Santa Clara 
Job Function: Design
  
Hiring Manager: Karthik C Mayasandra
 
 

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

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