Silicon Design Engineer - 95281

Location: Santa Clara, California, US

Company: Advanced Micro Devices

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What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

 

Silicon Design Engineer

The Role:

Central DFX (CDFX) is a centralized ASIC design group within AMD’s Technology and Engineering organization. The group consists of design teams located in several AMD locations in North America and Asia. It is primarily responsible for architecture, design, and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for leading edge AMD products for Server, Client, Discrete-GPU, APU and Automotive field.

The Person:

As an Silicon Design Engineer, you will be working with a team with varied strengths of design engineers and managers from various global design locations on design-for-test (DFT) design and implementation, tool and methodology development, project execution and continuous improvement initiatives. This role provides an excellent growth opportunity for robust individuals looking to make a difference. This is an exciting time to join the AMD team!

The following highlights a successful candidate:

  • Demonstrated logic design skills and project execution experience
  • Good understanding of Verilog language, clock crossing (CDC) and Static Timing Analysis (STA)
  • Basic knowledge about DFT and DFD
  • Excellent verbal and written communication and interpersonal skills
  • Self-starter, driven and focused with a dedication to meeting deadlines
  • Has an aptitude to thrive in a fast-paced multi-tasking environment
  • Used to working independently, and yet can work collaboratively with various levels and organization functions.

Key Responsibilities:

  • Working with a multi-discipline and international team of engineers on design-for-test (DFT) architecture, design, tools, and methodology initiatives
  • Writing RTL design in Verilog per micro-architectural specifications
  • Writing and maintain design specifications
  • Working with team performing RTL integration, synthesis, equivalency checking, timing analysis and closure including defining design constraints

Preferred Experience:

  • Demonstrated ASIC design experience
  • Proven technical leadership and works well with cross-functional teams
  • Excellent communication and interpersonal skills
  • Experience in complex ASIC design (multi-million gates) in DFT/DFD techniques such as JTAG/IEEE standards, scan and ATPG, on-chip test pattern compression and at-speed testing using PLL, memory BIST and repair, logic BIST, power-gating, on-chip debug logic, testing of high speed SerDes IO and analog design
  • Solid understanding and experience in Verilog simulator and waveform debugging tools, proficiency in debugging both RTL and gate level simulations
  • Experience in solving logic design or timing issues with integration, synthesis, and PD teams
  • Good working knowledge of UNIX/Linux and scripting languages (e.g., TCL, c-shell, Perl), C++ programming
  • Knowledge in EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis
  • Knowledge of ATE and digital IC manufacturing test is a plus
  • Knowledge in using emulator for ATPG pattern verification is a plus
  • Knowledge in ARM AXI protocol is a plus

Academic Credentials:

  • Minimum B.Sc in Electrical or Computer Engineering (or equivalent)

Location:

Santa Clara, CA

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers and will consider all applicants without regard to race, marital status, sex,

 

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Requisition Number: 95281 
Country: United States State: California City: Santa Clara 
Job Function: Design
  

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

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