SMTS Silicon Design Engineer

Location: Santa Clara, California, US

Company: Advanced Micro Devices

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What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

Physical Design Engineer - Graphics

 

  • Responsible for leading the pre-silicon Graphics IP implementation and PPA attainment.
  • Responsible for PPA attainment and improvement through synthesis and execution flows that starts with RTL coding and ends with the delivery of a netlist package ready for physical design.
  • Responsible for synthesis, timing, area improvement, floorplanning, clock methodology and power optimization.
  • Work in collaboration with Frontend RTL owners and Physical Design Engineers in block level planning and PPA attainment.

 

REQUIREMENTS:

 

  • Experience in complex ASIC Design.
  • Direct experience in implementation of Graphics/Video IP’s is plus.
  • Have in depth knowledge of entire design process from Design specification, defining architecture, micro-architecture, RTL design and functional verification, synthesis, Physical Design, Timing closure, Tape-out, and post-Si debug.
  • Have hands-on experience in Design implementation, synthesis, STA, clock skew optimization, and P&R activities.
  • Physical Design exposure required.
  • Perform Synthesis and PPA optimization tasks such as RTL tuning, flow parameter tuning, floorplan optimization, design storage optimization, power optimization, congestion resolution and maximize design utilization.
  • Some exposure to DFT is a strong plus.
  • Work with Physical Design team on Floor Plan, budgeting, timing closure, Signal Integrity, ECO flows, Power analysis etc.
  • Should have expertise in: Fusion compiler, Design Compiler, ICC2 or Innovus and  Primetime, . Good knowledge of datapath compilers is required.
  • Should have proficiency in flow development and scripting.
  • Expertise in Perl and Tcl is a must.
  • Should be able to work closely with RTL Designers and Backend Physical Design teams across multiple sites.
  • Must have good communication & Analytical thinking skills.

 

EDUCATION:

  • Masters in CS/EE with relevant course work and project background with 12+ years of experience, or Bachelors with 14+ years of experience

 

#LI-PH1



Requisition Number: 79443 
Country: United States State: California City: Santa Clara 
Job Function: Design
  

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

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