Physical Design Engineer - 95403

Location: Santa Clara, California, US

Company: Advanced Micro Devices

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What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

TITLE : Physical Design Engineer

 

THE ROLE : This is a Physical Design Engineering role that will require to take the design from RTL to GDS with syntheis, Place n Route, timing and Physical Verification

 

THE PERSON : Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams

 

RESPONSIBILTIES :

This engineer will work on high speed multi-gigabit SerDes PHY designs. This includes automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications, automated design flows for clock tree synthesis, clock and power gating techniques, buffer/repeater insertion, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. You will also support floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery.

 

PREFERRED SKILLED SETS :

Major in EE, CS or related, Master Degree with 3+ years or Bachelor with 5+ years working experience, preferably with high speed multi-gigabit SerDes PHY designs or other high performance IP designs
Experience in automated synthesis and timing driven place and route of RTL blocks (Verilog experience preferred) for high speed datapath and control logic applications
Experience in automated design flows for clock tree synthesis, clock and power gating techniques, buffer/repeater insertion, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction
Strong background in digital circuit techniques, efficient and robust implementation topologies for logic functions, logic optimization, and transistor level circuit topologies for high speed, low power applications
Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery
Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation
Versatility with scripts to automate design flow, simulation test benches, and quality checks
 

 

EDUCATION :

Major in EE, CS or related, Master Degree preferably with high speed multi-gigabit SerDes PHY designs or other high performance IP designs

 

LOCATION :

Santa Clara, CA

*LI-CS1



Requisition Number: 95403 
Country: United States State: California City: Santa Clara 
Job Function: Design
  

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

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