Physical Design Engineer

Location: Santa Clara, California, US

Company: Advanced Micro Devices

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What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

THE ROLE :

* Physical  Design Engineer to be part of a graphics PD team and lead the work.

 

KEY RESPONSIBILITIES:

• Full chip and block level timing closure for various stages of the entire design process (RTL, Synthesis, Place and Route and STA Signoff)

• Enhance and maintain all STA flows and methodology for multiple designs and across different technologies

• Work on all aspects of timing closure including Design rule checks , constraint validation , Noise analysis etc

• Work with various IP owners in developing and refining STA constraints for both full chip and block level.

 

Preferred Experience :

* Over 6 years experience with  ASIC Physical Design from RTL to GDSII

* Hands-on experience in all aspects of timing closure in high-performance designs using sub-micron technologies.

* Expertise in STA tools (such as Primetime) and methodologies for timing closure with a good understanding of OCV, noise, cross-talk, and cross-corner variation.

* Comfortable constraining timing paths using SDC and TCL.

* Familiar with creating functional and timing ECOs and verifying logical equivalence using Formality.

* Exposure to RTL, synthesis, logic equivalence, DFT, floor-planning, and backend-related methodology and tools such as ICC2 and Fusion Compiler.

* Basic understanding of scripting languages (Python and Perl) and design automation using TCL.

* Knowledge of SSB timing is a plus.

* Strong communication skills and can accurately describe issues cross-functionally to different teams (RTL design, verification, DFT, AMS) at an appropriate level of detail

 

Academic Credentials:

MSEE or MSCE

#LI-DC3

 


Requisition Number: 172541 
Country: United States State: California City: Santa Clara 
Job Function: Design
  

Benefits offered are described here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

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