Static Timing Analysis (STA) Engineer 95405

Location: Santa Clara, California, US

Company: Advanced Micro Devices

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What you do at AMD changes everything 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

TITLE : STA Engineer


THE ROLE : This is a Physical Design Engineering role that will require to take the design from RTL to GDS with syntheis, Place n Route, timing and Physical Verification


THE PERSON : Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams



This engineer will work on high speed multi-gigabit SerDes PHY designs. This includes automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications, automated design flows for clock tree synthesis, clock and power gating techniques, buffer/repeater insertion, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. You will also support floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery.



Hands-on experience in all aspects of timing closure in high-performance designs using sub-micron technologies.

• Expertise in STA tools (such as Primetime) and methodologies for timing closure with a good understanding of OCV, noise, cross-talk, and cross-corner variation.

• Comfortable constraining timing paths using SDC and TCL.

• Familiar with creating functional and timing ECOs and verifying logical equivalence using Formality.

• Exposure to RTL, synthesis, logic equivalence, DFT, floor-planning, and backend-related methodology and tools such as ICC2 and Fusion Compiler.

• Basic understanding of scripting languages (Python and Perl) and design automation using TCL.

• Knowledge of SSB timing is a plus.

• Strong communication skills and can accurately describe issues cross-functionally to different teams (RTL design, verification, DFT, AMS) at an appropriate level of detail



Major in EE, CS or related, Master Degree preferably with high speed multi-gigabit SerDes PHY designs or other high performance IP designs



Santa Clara, CA


Requisition Number: 95405 
Country: United States State: California City: Santa Clara 
Job Function: Design


AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

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