System Architecture & Modeling Engineer

Location: Santa Clara, California, US

Company: Advanced Micro Devices

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What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

The candidate will be a member of the high performance SerDes and DDR design team supporting the system simulation and implementation of high-speed SerDes IPs and advanced DDR systems. The focus of the activity will be centered around the modeling of the critical high-speed analog and digital blocks, definition of algorithms for calibration, adaptation, equalization, and development of abstracted models for link performance simulations.

 

Responsibilities will include:

  • Contribute to the modeling of various state-of-the-art, high-speed (32-64Gbps) analog/mixed-signal blocks for SerDes PHYs, especially in the PAM4 area
  • Contribute to architectural models of the Serdes and DDR projects and develop models for link-level performance (BER, eye-opening) simulation of the PHY and application of the same to the development and optimization of performance.
  • Documentation of algorithms and guidance of Analog, Digital, Firmware and Verification teams on the implementation/verification of the same 
  • Work closely with various disciplines, especially Analog Mixed Signal design, Digital Design and Firmware, as well as Design Verification to ensure optimal implementation of the overall PHY architecture and algorithms and full coverage of the features
  • Participate to the definition of development flows that improve efficiency and quality of execution 

 

The successful candidate will possess:

  • A proven successful track record in micro-architecture, design, or modeling for SERDES, DDR or related projects.
  • Solid and hands-on knowledge of algorithms and adaptation/calibration/ clock and data recovery techniques for high-speed PHY. Experience in higher modulation such as PAM4 will be an asset.
  • Solid knowledge of industry-standard tools and best-in-class practices for PHY modeling, both in terms of abstracted models (e.g. Matlab/Simulink/Python) and detailed real number modeling, i.e., System-C and SystemVerilog based modeling techniques.
  • Good knowledge in high-speed SerDes design (signaling/equalization techniques, analog/mixed-signal circuit design, and signal integrity).
  • Ability to dig into circuits and RTL or FW code to understand the detailed implementation
  • Analytical thinking and inventive spirit in combination with a solid understanding of risks and risk mitigation
  • Strong/effective communication skills
  • Enthusiastic team-first mentality

 

Education:

  • BS or MS (PhD is preferred)

 

AMD employees who will be working onsite at an AMD US facility, are encouraged to provide proof of being fully vaccinated against COVID-19 upon their start date. This is for the safety of our employees, and to permit AMD to be prepared in the event the stay on Executive Order 14042: Ensuring Adequate COVID Safety Protocols for Federal Contractors is lifted. AMD is not requiring exemption / accommodation submittals at this time.

 

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Requisition Number: 162861 
Country: United States State: California City: Santa Clara 
Job Function: Design
  

Benefits offered are described here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

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