Senior ASIC Verification Engineer - 74764

Location: Santa Clara, US

Company: Advanced Micro Devices

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What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

The Unified Memory Controller(UMC) is an IP that delivers into all SOCs that are shipped by AMD's Radeon Technology Group. We deliver discrete GPUs, Data Center GPUs and Game Console APUs using a flexible controller design as the base for all our IP. Our IP supports all versions of GDDR and HBM Dram Technologies. We are looking for a design verification engineer in the Dram Controller IP at AMD's Santa Clara Design Center. You will be working in a fast-paced, complex environment where you will be challenged to provide elegant, robust solutions for increasingly complex features.

There are many challenges as we continuously add features, refine our design and enhance our testbench to take on the next generation of projects 

 

As a Senior verification team member, your responsibilities would include  

  • Develop quality, timely and cost effective solutions independently.
  • Contribute to testbench architecture and infrastructure, helping to build a reliable, scalable, and flexible verification environment
  • Develop/Enhance UVM testbench components like test-cases, monitors, scoreboards, sequencers, and sequences for new features
  • Drive debug and closure of regression signatures using waveform viewer and output files; and collaborate with the RTL designers and testbench owners to fix bugs.
  • Mentor junior engineers by guiding them to think through complex problems and develop robust solutions
  • Contribute your experience to our environment, allowing us to deliver a better quality IP

 

Experience with Verilog, System Verilog, and UVM is a requirement

- Requires strong Programming and debug skills.

- Experience with DRAM controllers and ddr phys is a plus. 

- Requires strong communication skills and the ability to work independently as well as in a cross-site team environment.

- Strong Computer Architecture knowledge

 

#LI-GK1



Requisition Number: 74764 
Country: United States State: California City: Santa Clara 
Job Function: Design 

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.


Nearest Major Market: San Jose
Nearest Secondary Market: Palo Alto

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