Senior Design Verification Engineer - 77743

Location: Santa Clara, California, US

Company: Advanced Micro Devices

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What you do at AMD changes everything 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

Senior Design Verification Engineer


The Unified Memory Controller (UMC) is an IP that delivers into all SOCs that are shipped by AMD's Radeon Technology Group. We deliver discrete GPUs, Data Center GPUs and Game Console APUs using a flexible controller design as the base for all our IP. Our IP supports all versions of GDDR and HBM Dram Technologies. We are looking for a senior design verification engineer in the Dram Controller IP at AMD's Santa Clara Design Center. You will be working in a fast-paced, complex environment where you will be challenged to provide elegant, robust solutions for increasingly complex features. There are many challenges as we continuously add features, refine our design and enhance our testbench to take on the next generation of projects.


  • This is a very high visibility role, involving communication across various geographies supporting various stakeholders.
  • Strong Design Verification skills - problem-solving, debugging skills and attention to details
  • Good interpersonal skills (verbal and written) for mentoring junior engineers, generating consensus for improvements in verification methodology
  • Well rounded experience in SoC / IP teams 



  • Perform Functional Verification for new features based on project requirements
  • Create/Implement Verification Test plans that are detailed and well thought out.
  • Write scalable, portable, flexible verification component using standard methodology and coding guidelines
  • Implement Functional Coverage through cover-points and SVAs
  • Ability to dig into the design / testbench to debug complicated simulation failures
  • Mentor junior engineers so they can mature into strong contributors
  • Suggest details improvements to existing TB components / processes and implement them
  • Develop UVM based checker/monitor/sequence for new features verification
  • Contribute to overall health of the test bench / simulation environment



  • Minimum of 5 years of proven verification experience on ASIC projects
  • Strong Computer Architecture knowledge
  • Experience working in a team environment through the ASIC Project lifecycle from Planning to Tape Out
  • Experience with DRAM controllers and DDR Phys is a plus. 
  • Must have strong background in Verilog, System Verilog, OO coding techniques
  • Must have experience working with Synopsys VCS or equivalent
  • Strong experience working with UVM, OVM or equivalent desired
  • Must have experience working with assertions and functional coverage
  • Experience with scripting languages, Ruby/Python/Tcl/BASH/etc. desired



Requisition Number: 77743 
Country: United States State: California City: Santa Clara 
Job Function: Design


AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

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