Digital Silicon Validation and Design Engineer - 129842

Location: Santa Clara, California, US

Company: Advanced Micro Devices

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What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

THE ROLE:

We are searching for a Digital Silicon Validation and Design Engineer to join the GDDR PHY design team.  This is an exciting opportunity to be a member of the Memory IO design team responsible for defining, specifying, and implementing RTL for the next generation of high-speed GDDR and inter-chip IO IP for AMD’s graphics and semi-custom products.

 

THE PERSON:

The successful candidate will possess:

  • Excellent analytical and problem-solving skills along with attention to details
  • Must be a self-starter, able to drive tasks independently and efficiently to completion
  • Strong/effective communication skills
  • Enthusiastic team-first mentality
  • Ability to provide mentorship and guidance to junior engineers
  • Relevant academic background and at least 7 years progressive experience

 

KEY RESPONSIBILITIES:

  • Pre-silicon digital validation utilizing a digital ASIC simulation environment
  • Enhancement of digital design to optimize for performance (speed, power, etc.) and behavioral modeling of custom circuits with SystemVerilog
  • Define and drive the digital design post-silicon test plan with support from design, circuit and architecture teams
  • Lead the digital design silicon bring up effort by executing against the test plan and tracking progress
  • Work with other debug teams and design owners to drive critical issues to closure
  • Enhance existing diagnostics utilities and tools to help streamline bring up activities
  • Define and drive new flows to improve post-silicon efficiency
  • Recommend improvements, optimization and power saving enhancements

 

PREFERRED EXPERIENCE:

  • Proven experience in silicon bring up, debug and support for mixed signal IP
  • GDDR and/or HBM experience is highly desired. DDR and high speed SERDES experience is a plus.
  • Digital design experience with SystemVerilog highly desired
  • Strong programming/scripting skills (C/C++, Python, Perl, Ruby) is a must
  • 7+ years of experience in digital design debug and silicon support

 

ACADEMIC CREDENTIALS:

  • Relevant academic background (Master’s degree preferred)

 

Location: Santa Clara, CA, - Austin, TX,- Boxborough, MA, - Rochester, NY, USA

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Requisition Number: 129842 
Country: United States State: California City: Santa Clara 
Job Function: Design
  
Hiring Manager: Damon Tohidi
 

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

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