Silicon Design Engineer 2- 116146

Location: Santa Clara, California, US

Company: Advanced Micro Devices

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What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

Title: ASIC Logic Design & DFT Methodology Engineer 

 

The Role:

The mixed-signal IP design team handles high-speed Serdes & memory Phy design and delivers it to SoC. The focus is on enabling high-quality Design-for-test (DFT) solutions both for digital and analog logic. We are seeking a candidate that has a blend of talents and experience

 

Key responsibilities:

  • Be a key member of a team that can create timing SDCs on mixed-signal design and DFT logic
  • Based on the knowledge of DFT the effort is required to run test coverage analysis using AMD defined processes
  • Develop/improve on flows for scan timing, creating SDC constraints, debugging the design for violations, creating CDC waivers
  • Drive debug and closure of issues with the cross-functional teams.
  • Develop quality, timely, and cost-effective solutions to independently drive timing-related issues.
  • Create a methodology for Fault simulation on designs that lacks the test coverage targets.
  • Developing, improving, and maintaining scripts and documentations as vital

 

Preferred Experience:

  • Exposure of computer architecture, ASIC design and Design-for-test methodology is required.
  • Good understand of RTL design (Verilog/System Verilog)
  • Strong debug, analytical and problem-solving skills with a passion
  • Proficiency with Industry Standard tool for Scan, ATPG, & MBIST
  • Programming/Scripting in Perl, Tcl, & Make is desired

 

Academic Credentials:

  • MS in ECE/EE or equivalent

 

#LI-AA1



Requisition Number: 116146 
Country: United States State: California City: Santa Clara 
Job Function: Design
  

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

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