Sr. Logic Design Engineer

What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

Sr. Logic Design Engineer - 134913

THE ROLE:
An integral member of the Circuit Technology Team that plays a significant role in ensuring the quality of designs through structured DFT techniques.  We seek a Sr. Logic Design Engineer with experience in Test who can lead the DFX architecture for new IP development.

THE PERSON

For this individual contributor role the successful candidate will be a hands-on execution specialist with:

• Strong Logic Design and background in Test
• Excellent analytical and problem-solvin skills, along with attention to detail
• Ability to drive tasks independently and efficiently to completion
• Strong/effective communication skills
• Enthusiastic team-first mentality

KEY RESPONSIBILITIES

• Develop test structures which can be used for functional tests as well (e.g. JTAG to AXI/AHB bridge, faster SRAM loading architecture etc)
• Interfacing with the IP design teams to ensure DFT design rules and guidelines are met
• DFT architecture development/definition for Circuit technology IPs (High speed SerDes etc)
• DFT IP development, RTL coding and integration to support functional tests as well as ALL   structural tests for the IP, post silicon support
• SDC development and delivery for shift/capture mode
• Compression RTL generation and integration into the DFT wrapper
• Boundary Scan integration into the DFT wrapper
• Ownership of inserting all the test structures (scan wrappers for scan isolation, MBIST, OCCs for test clocking, silicon debug features etc)
• Developing, enhancing and maintaining scripts and documentation as necessary
• Post silicon debug and support

PREFERRED EXPERIENCE 

• Knowledge of DFT basics such as JTAG standards (1149.1/P1687/P1500), Memory testing, industry standard bus protocols : AXI, AHB etc.
• Strong logic design skills, knowledge of verilog, system Verilog
• Understanding of DFT fundamentals such as scan, test clocking, BIST etc is preferred

ACADEMIC CREDENTIALS

• Minimum BS (EEE) 

LOCATION

Santa Clara, CA

#LI-MS2

Requisition Number: 134913 
Country: United States State: California City: Santa Clara 
Job Function: Design  

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