Validation Systems Engineer -81605

Location: Santa Clara, California, US

Company: Advanced Micro Devices

Apply now

Apply for Job


What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

Title : Systems Validation Engineer

 

The Role : Candidate will be responsible for comprehensive electrical & functional test plans for the processor interface validation of processors. The candidate will execute electrical & functional test plans for client processors using FPGA hardware & software validation tools, oscilloscopes, & logic analyzers. Provide detailed input into the platform definition & review of platform designs used in the silicon validation of new processors. 

 

The Person : Requires good written and oral communication skills with a Demonstrated ability to communicate with a variety of engineering disciplines and management.

 

Responsibilities :

- pre silicon validation via FPGA for emulating the system

- post silicon validation, lab bring up and debug

- Root cause analysis and resolving system issues

 

Preferred Experience & Skill Set:

 

  • Requires experience and demonstrated technical expertise in the development & execution of platform level electrical & functional test plans. Platform level experience with high speed I/O interfaces
  • Experienced in FPGA development, Synthesis with logical & physical constraints, Timing closure and Place and Route in FPGA
  • Requires experience and demonstrated technical expertise in the debug of processor & PC platform I/O interfaces.
  • Demonstrated experience with or knowledge using oscilloscopes, reading schematics and layout documentation, and MS Windows and Office applications.
  • Requires good written and oral communication skills; Demonstrate the ability to communicate with a variety of engineering disciplines and management.

 

EDUCATION: B. S. in Electrical Engineering or Computer Engineering

*LI-AP1



Requisition Number: 81605 
Country: United States State: California City: Santa Clara 
Job Function: Design
  

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

Apply now

Apply for Job

Share this Job