Video IP Design Engineer

Location: Santa Clara, California, US

Company: Advanced Micro Devices

Apply now

Apply for Job

What you do at AMD changes everything 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

Video IP Design Engineer

The Role:

We, Video HW IP/Solution Group at AMD Markham site, are looking for a Video IP Design Engineer who will work in an established IP team. The role will require the candidate to initially acquire background knowledge of VCN IP core system blocks. Subsequently, the candidate will be responsible to actively collaborate with various team members to understand design requirements, drive block level low power methodology development, IP level bring-up, timing/area/performance trade-offs throughout the design cycle. In addition, the engineer will work with relevant FW developers to complete IP solution validation, regressions and provide verification consultation to downstream video deployment/SoC teams.

The Person:

Will collaborate with the Video IP design team to produce forward-thinking design functionality for state of the art components. With your analytical mind, you will be problem-solving in a fast-paced work environment on multiple projects. If you possess the ability to adapt quickly to rapid technology changes you will excel at AMD!

Key Responsibilities:

  • Draft block level design requirements and micro-architecture specifications.
  • Perform block level micro-architecture design, RTL implementation and power/area efficient designs.
  • Define block programming model and interact with firmware/software team to bring-up functionality at IP and SOC levels.
  • Perform design metrics checks such as LINT, CDC, synthesis, static timing analysis, and power analysis.
  • Work with verification engineers to define test plan and functional verification coverage.
  • Engage verification closure, including test debug, code coverage and functional coverage review and sign-off.
  • Responsible for bug fixes, including engineering change order (ECO) implementation and verification through formal verification
  • Work with SoC DV team to debug test failures at IP and chip level.

Preferred Experience:

  • Minimum 7 years of proven ASIC/FPGA design and verification experience.
  • Knowledge of SoC design flow from specification, implementation, to verification and Silicon debug/validation.
  • Proven RTL design experience using System Verilog and driving low power design methodology across block level/IP level.
  • Experience using UVM methodology in verification is an asset
  • Familiar with CAD tools of simulation, RTL synthesis, static timing analysis, power analysis using PTPX/PA and formal verification.
  • Handy in Linux script languages such as Perl, Python, Ruby or/and shell languages.
  • Prior team, technical leadership or mentorship are phenomenal valuable assets
  • Good teammate and communicator
  • Basic video codec knowledge is definitely a plus.
  • Proficient in simulation, debugging, Synthesis, lint and CDC tools.

Academic Credentials:

  • BS degree in Electrical or Computer Engineering
  • MS degree preferred



Requisition Number: 168001 
Country: United States State: California City: Santa Clara 
Job Function: Design

Benefits offered are described here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

Apply now

Apply for Job

Share this Job