78946_Design Verification Engineer

Location: Shanghai, Shanghai, CN

Company: Advanced Micro Devices

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What you do at AMD changes everything 


At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 


Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

 

THE ROLE:

AMD NBIO (North Bridge IO) team delivers industry leading high-performance interconnects IP subsystem for all AMD products including dGPU, APU, Server and Game consoles. You'll be working with the global team on NBIO container assembly and verification, NBIO subsystem features bring up, integrating NBIO subsystem to SoC and provide technical support to various global SOC teams.

 

THE PERSON:

NBIO container deployment lead, responsible for NBIO sub IP hook up, container assembly, container design, SoC integration and SoC DV support.

 

KEY RESPONSIBILITIES:

 

  • Lead the effort to pull drops from NBIO sub IP teams, assemble NBIO container drop, and bring up features and do basic verification.
  • Lead the effort to integrate NBIO subsystem to SoC and provide support to SoC team.
  • Maintain NBIO depot and optimize the depot to serve global NBIO DV/Design teams.
  • NBIO technical contact window to SoC team.
  • NBIO subsystem level test plan and SOC test plan consulting.
  • NBIO DV/Deployment flow implementation.

 

PREFERRED EXPERIENCE:

 

  • Complex IP/ASIC/SOC design verification, direct experience in IP/SOC or Processor (CPU or GPU) or Industry bus standard (PCI-e, HT, USB, DDR, DisplayPort)
  • Solid background with ASIC design verification flow and multiple ASIC tape out experience
  • Solid knowledge on SystemVerilog, C/C++, Verilog
  • Solid knowledge on scripting language like perl, python, ruby
  • Solid knowledge on UVM/OVM
  • Solid background with hardware verification methodologies such as coverage-based verification methodology with the use of hardware assertions (PSL or SVA)
  • Knowledge on High speed IO/PCIE is a big plus
  • Experience in SoC integration is a big plus
  • Experience in project management is a big plus
  • Fluent verbal English for technical discussion with global team

 

ACADEMIC CREDENTIALS:

Candidate is preferred to be MSEE with minimum of 5 years, or BSEE with minimum of 7-year experience in digital ASIC/SOC design verification.

 

LOCATION:

Shanghai

 

APPLY:

Email to bella.yu@amd.com

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AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers and will consider all applicants without regard to race, marital status, sex, age, color, religion, national origin, veteran status, disability or any other characteristic protected by law. EOE/MFDV



Requisition Number: 78946 
Country: China State: Shanghai City: Shanghai 
Job Function: 
Design  

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