Sr. Silicon Design Engineer

Location: Shanghai, Shanghai, CN

Company: Advanced Micro Devices

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What you do at AMD changes everything 


At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 


Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

 

THE ROLE:

AMD NBIO (North Bridge IO) team delivers industry leading high-performance interconnects IP for all AMD products including dGPU, APU, Server and Game consoles.  NBIO global operates seamless from China, North America and Europe.

PCIe IP is one of the most important IP in all AMD’s projects. Shanghai PCIe team contributed a lot on the first PCIe Gen4 product and are working on Gen5 product. So, this role provides a great opportunity for working on the most advanced PCIe technology.

As a global team, the candidate also has opportunities to travel to Canada, Serbia or America to attend some technique conferences, face to face to talk with global technique leads.

THE PERSON:

  Good communicate skill, co-work spirit, strong self-learning and adaptability are preferring.

KEY RESPONSIBILITIES:

* PCIe IP PV(performance verification)

  • Work with IP/SOC PV architect to finalize the PCIe PV design requirement.
  • Maintain/update PV test suite according to PCIe PV design requirement.
  • Need deep insight into DUT when debugging to catch potential design limit.
  • Signoff PCIe IP PV work.
  • Do PV automation initiative to improve testing efficiency.

PREFERRED EXPERIENCE:

  1. At least 3 years’ experience in Complex IP Design Verification is required.
  2. Work experience in Industry bus standard (e.g. PCIe/USB/AXI) is preferred.
  3. Performance Verification work experience is preferred.
  4. Good knowledge of Verilog/C/C++/System C/System Verilog.
  5. Good knowledge of at least one verification methodology. UVM is preferred
  6. Good at both Oral English and written English
  7. Good knowledge of script, Perl/Makefile/TCL is preferred

ACADEMIC CREDENTIALS:

MSEE within 3-5 years, or BSEE within 4-6 years’ experience in digital ASIC/SOC design verification

LOCATION:

Shanghai

 

APPLY:

Email to zoe.wu@amd.com

#LI-JW1



Requisition Number: 87501 
Country: China State: Shanghai City: Shanghai 
Job Function: 
Design  

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