87795_CIT IP DV Engineer

Location: Shanghai, Shanghai, CN

Company: Advanced Micro Devices

Apply now

Apply for Job


What you do at AMD changes everything 


At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 


Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

 

THE ROLE:

CIT (Chiplet Interconnect Technology) team delivers industry leading high-performance interconnects IP for all AMD products including dGPU, APU, Server and Game consoles. CIT includes AMD Internal links for on-chip connection and Machine Learning. You'll be working with the global team Architects/Designers/DV to verify key Chiplet IPs and ensure the high-quality delivery.

 

THE PERSON:

People who have the passion to work on leading edge technology, who have solid verification capability and communication skills will be successful in this role.

 

KEY RESPONSIBILITIES:

  • Work on CIT IP and subsystem level verification
  • Closely working with Design/Architecture team to develop new verification components
  • Responsible for IP features verification plan and verification closure, closely work with Designers and Architects to ensure IP verification completes  

 

PREFERRED EXPERIENCE:

  • Major in EE, CS or related, 5+ years working experience
  • Solid background with ASIC design verification flow and multiple ASIC tape out experience
  • Solid knowledge on UVM, SystemVerilog , Verilog
  • Knowledge on script language like perl, python, ruby is a plus
  • Knowledge on High speed IO/PCIE is a plus
  • Fluent vocal English for technical discussion among global team

 

ACADEMIC CREDENTIALS:

  • Candidate is preferred to be MSEE with 4~9 years, or BSEE with minimum of 5-years’ experience in digital ASIC/SOC design verification.

 

LOCATION:

Shanghai, China


AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers and will consider all applicants without regard to race, marital status, sex, age, color, religion, national origin, veteran status, disability or any other characteristic protected by law. EOE/MFDV

#LI-JW1



Requisition Number: 87795 
Country: China State: Shanghai City: Shanghai 
Job Function: 
Design  

Apply now

Apply for Job

Share this Job