SMTS Silicon Design Engineer

Location: Shanghai, Shanghai, CN

Company: Advanced Micro Devices

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What you do at AMD changes everything 


At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 


Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

 

Low Power Design Engineer

 

THE ROLE:

Work in Shanghai RPPG group of RTG. We keep improving PPA of every graphic chip and especially focus on their power performance. As the team member, you will take the responsibility to provide accurate power reporting flow, power optimization solution of block design, exploration on power saving feature of EDA tools and so on. You’ll have access to cutting-edge technology/tools/process. Join us if you have much interest in power optimization or you want to develop your competence in a wide range of block design/DV/Synthesize/P&R/….

 

THE PERSON:

Low power design engineer who has much interest in low power optimization will be involved in many aspects of IC design. Work closely with RTL Design team, design verification team and backend physical design teams across multiple sites. Good communication skill and team spirit. Strong issue debugging capability

 

 

KEY RESPONSIBILITIES:

  • Work with global Front-End design team, physical design team, methodology team for improving large scale ASIC chips performance/watt performance.
  • Defining low power methodology of block design implementation
  • Driving Low power optimization cross multi-IP/SOC teams
  • Develop power simulation flow for power reporting and debug the abnormal data
  • Termly deliver, check and analyze power report

PREFERRED EXPERIENCE:

  • the architecture of the graphics IP or functional block preferred
  • Wide knowledge of entire IC process from Design specification, defining architecture, micro-architecture, RTL design and functional verification, synthesis, Physical Design, Timing closure, Tape-out, and post-Si debug
  • Hands-on experience on one of the following areas: driving Low power design / defining low power methodology / Block or Chip level RTL Design / block or Chip level design verification.
  • Design implementation (from synthesis to P&R) experience preferred.
  • Expertise in the knowledge of how to get power data desired
  • Having proficiency in flow development and scripting (PERL, TCL, PYTHON, SHELL) is a strong plus.

 

 

 

ACADEMIC CREDENTIALS:

  • Master with 3 years or Bachelor with 5 years working experience in ASIC area

 

 

LOCATION:

Shanghai

#LI-NJ1


AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers and will consider all applicants without regard to race, marital status, sex, age, color, religion, national origin, veteran status, disability or any other characteristic protected by law. EOE/MFDV



Requisition Number: 79836 
Country: China State: Shanghai City: Shanghai 
Job Function: 
Design  

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