MTS Silicon Design Engineer

Location: Shanghai, Shanghai, CN

Company: Advanced Micro Devices

Apply now

Apply for Job

What you do at AMD changes everything 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.


IP Design and Verification Engineer



It is a must that the candidate has one or more of the following experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, USB(4.0/3.x/2.0; HSIC/host/device/OTG;PD slave) system, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS/SSD, Legacy IPs (ESPI/SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I3C/I2C/UART), Ethernet, JTAG, etc.



The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, specialized knowledge plus broad technical knowledge that facilitates integrative thinking, driving execution of quality and timely result, be capable to solve complex, novel and no-recurring problems and decision-making on critical technical areas.



  • Work with team members and apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market for Southbridge
  • Provide the technical leadership to the DV team for the new Southbridge project
  • Work independently on various DV tasks and providing technical guidance to the DV team.
  • Be involved technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup



  • Master’s in electrical engineering, computer science or related
  • Good understanding on ASIC design verification flow
  • RTL coding with Verilog/System Verilog and familiar with front-end design flow
  • UVM/SV verification project experience
  • C/C++ and other scripts (Perl/Ruby/Python) programming experiences
  • Knowledge on SVA, functional coverage, low power verification, formal verification, etc.
  • USB experiences is a plus



MSEE with minimum of 6 years, or BSEE with minimum of 8 years experiences in digital ASIC/SOC design verification



Requisition Number: 93705 
Country/Region/Location: China State/Province: Shanghai City: Shanghai 
Job Function: 

Apply now

Apply for Job

Share this Job