MTS Silicon Design Engineer

Location: Shanghai, Shanghai, CN

Company: Advanced Micro Devices

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What you do at AMD changes everything 


At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 


Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

 

THE ROLE:

You will design and build the SOC design which will be a key enabler for the SOC functional teams to begin simulation and netlist activities. Collaborate with the architectures, IP design, and Physical Design teams around the world to achieve first pass silicon success!

THE PERSON:

-   You should be excellent in problem solving, communication and projection!

Key responsibilities:

  • Collaborate and build alliances with IP development teams, SOC design and verification teams to build RTL models of complex SOC projects.
  • Analyze and tackle issues and challenges including AMD proprietary model build flow, simulation library development, IP interfaces and integration, top-level RTL development including connectivity and chip functions such as clocking, reset, and IO.
  • Corroborate design and feature enhancements, top-level chip latency and performance impact.
  • Conduct design integrity, quality and structural checks such as verilog lint checks, and power domain and clock domain checks as appropriate.
  • Work in partnership with front-end integration teams on synthesis of the SOC top-level netlist and collaborate with physical design on modifications to facilitate full-chip SOC construction

PREFERRED EXPERIENCE:

  • Experience in integrating and compiling complex SOC models with multiple proprietary and third-party IP
  • Industry standards for SOC and IP design, modeling and reuse
  • Experience in building project simulation libraries usable by IP and SOC teams throughout the design cycle.
  • Understanding of SOC data fabric architectures
  • SOC clocking and reset functionality
  • Verilog lint tools (VC_Lint) and verilog simulation tools (vcs)
  • Clock domain crossing tools (0-in)
  • Power domain checking tools (VC_LP)
  • Experience working with Design Verification teams on functional and performance verification
  • Good verbal and written communication skills
  • Verilog RTL design and simulation tools (VC_Lint, VCS)

ACADEMIC CREDENTIALS:

  •        BS in EE & CS.  MS preferred, with 5+ years’ experience.

 

LOCATION: Shanghai, Beijing.

 

#LI-JG2

 



Requisition Number: 97694 
Country/Region/Location: China State/Province: Shanghai City: Shanghai 
Job Function: 
Design  

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