Sr. Silicon Design Engineer

Location: Shanghai, Shanghai, CN

Company: Advanced Micro Devices

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What you do at AMD changes everything 


At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 


Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

 

NBIO Subsystem DV Engineer

 

THE ROLE:

AMD NBIO (North Bridge IO) team delivers industry leading high-performance interconnects IP for all AMD products including dGPU, APU, Server and Game consoles. NBIO global operates seamless from China, North America and Europe.

As a global team, the candidate also has opportunities to travel to Canada, Serbia or America to attend some technique conferences, face to face to talk with global technique leads.

 

THE PERSON:

Be good at communication and teamwork, self-motivated and with good work ethics.

 

KEY RESPONSIBILITIES:

  • NBIO Subsystem verification.
  • Work with global/local IP architects/designers to get a thorough understanding about each IP within NBIO container, like PCIe, IOHUB, nBIF/SHUB. Update NBIO Subsystem testcase and debug testcase for regression triage.
  • Work with global/local IP DV teams, to achieve NBIO Subsystem testbench excellence. 

 

PREFERRED EXPERIENCE:

  • Complex IP Design Verification, direct experience in IP/SOC or Processor (CPU or GPU).
  • Good knowledge of design verification methodology, familiar with UVM/OVM/VMM.
  • Good RTL coding with Verilog, test-bench coding with SystemVerilog.
  • Hands on experience of PCIe verification is a strong plus.
  • Have low power or power aware experience is a strong plus.
  • Have leading edge industrial high speed I/O verification, like CXL and USB4 is a strong plus.
  • Be good at script language, such as Perl, Python, Ruby, C Shell, Makefile.
  • Be good at both speaking and written English.

 

ACADEMIC CREDENTIALS:

  • MSEE within 4-7 years, or BSEE within 5-8 years’ experience in digital ASIC/SOC design verification

 

LOCATION:

Shanghai

 

APPLY:

Email to zoe.wu@amd.com


AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers and will consider all applicants without regard to race, marital status, sex, age, color, religion, national origin, veteran status, disability or any other characteristic protected by law. EOE/MFDV

 

#L1-JW1



Requisition Number: 114762 
Country/Region/Location: China State/Province: Shanghai City: Shanghai 
Job Function: 
Design  

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