IOMMU IP DV Engineer

Location: Shanghai, Shanghai, CN

Company: Advanced Micro Devices

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What you do at AMD changes everything 


At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 


Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

 

What you do at AMD changes everything

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, Immersive platforms, and the data center.

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

IOMMU IP DV Engineer

 

THE ROLE:

AMD NBIO (North Bridge IO) team delivers industry leading high-performance interconnects IP for all AMD products including dGPU, Machine Learning, APU, Server and Game consoles.  NBIO global operates seamless from China, North America, and Europe.

IOHUB sits in the center of all data paths, it includes 2 SUB-IP name as IOHub Core and IOMMU.   The IOHC (Input/Output Hub Core) is the core logic of IOHUB. The major IOHC function includes address decoding, PCIe config space shadow registers, INTx interrupt translation, memory access data path, etc. Shanghai IOHUB team is expanding and hiring MTS level design verification engineer focus on IOHC DV and project execution work.

 

 

THE PERSON:

Candidate will work as a MTS design verification engineer, co-operate with local engineers and co-work with global IOHUB team on IOHUB related features development, maintenance, and optimization. Candidate needs to have IP verification background and good English read/write capability.

 

 

KEY RESPONSIBILITIES:

  • IOHC new feature implementation
  • IOHC feature test plan and DRVR writer, implement the delta changes
  • Attend conference call for strategy alignment, status sync up etc. with global team
  • Features Sign-off

 

PREFERRED EXPERIENCE:

  • Global company working experience background, good read/write English capability
  • Complex IP/ASIC/SOC Design Verification, direct experience in IP/SOC or Processor (CPU or GPU) or Industry bus standard (PCI-e, HT) is preferred.
  • Good knowledge of UVM/Verilog/System Verilog.
  • Solid background with hardware verification methodologies such as coverage-based verification methodology with the use of hardware assertions (PSL or SVA), insights into random techniques.
  • Strong scripting languages (Python, Perl, Makefile, …) experience is plus.
  • Has X86 and PCIe knowledge is plus

 

ACADEMIC CREDENTIALS:

  • MSEE within 4+ years, or BSEE within 7+ years’ experience in digital ASIC/SOC design verification.

 

#L1-JW1



Requisition Number: 115103 
Country/Region/Location: China State/Province: Shanghai City: Shanghai 
Job Function: 
Design  

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