MTS Systems Design Engineer

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We care deeply about transforming lives with AMD technology to enrich our industry, our communities and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence, while being direct, humble, collaborative and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team.

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MTS System design Engineer

THE ROLE:

Processor silicon DDR interface feature enable, electrical test and debug engineer.  In this role, this senior level engineer will be part of a highly technical team that develops test plans, executes bring-up & feature enable, & debugs electrical issues in the memory sub-system of new processors.

THE PERSON:

The person needs to be well self-motivated for deliveries and innovation, strong technical background on DDR interface, also with good communication skills.

KEY RESPONSIBILITIES:

• Provides DDR technical leadership in the development of new test & validation features
• Closely interacts with silicon design (DRAM controller and phy) in test execution & debug, as well as in feature definition for future product generation
•  Writes comprehensive electrical & functional test plans for the memory validation of processors
•  Executes electrical & functional test plans for AMD processors using hardware & software validation tools, oscilloscopes, & logic analyzers.
• Debug of electrical & functional issues of the memory sub-system of new processors
• Provides detailed input into the platform definition & review of platform designs used in the silicon validation of new processors. 

REQUIRED EXPERIENCE:

•  Requires experience and demonstrated technical expertise in the development & execution of platform level electrical & functional test plans. DDR4(5)/LPDDR4(5) Memory test experience on electronic components such as uProcessors would be considered a big plus.  
•  Requires extensive hands-on experience and demonstrated technical expertise in the debug of I/O interfaces such as DDR
• Familiar with DDR signal measurement, reading schematics and layout documentation
• Requires good written and oral communication skills.  
• Familiar with Python, Ruby, Perl language.

PREFERRED EXPERIENCE:

• Working knowledge of lab equipment such as oscilloscopes, logic analyzers and protocol analyzers
• Self-organizing and the ability multitask based on priorities
• Scripting and automation tool development is a plus.

• Linux environment validation or development experience is also a great plus

  ACADEMIC CREDENTIALS:

• Bachelor with 6+ years’ experience.
• Master with 3+ years’ experiences.

LOCATION:

Shanghai

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Requisition Number: 172162 
Country/Region/Location: China State/Province: Shanghai City: Shanghai 
Job Function: Design