Manager Silicon Design Engineering - ISP Design

Location: Shanghai, Shanghai, CN

Company: Advanced Micro Devices

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What you do at AMD changes everything 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.


ASIC Design Manager (Image Signal Processor)




AMD Image Signal Processor (ISP) team has immediate opening of ASIC design manager. The successful candidate will be working with global teams and lead local design team to develop ISP IP and deliver to AMD SoC projects.




The candidate would be hired in as design manager, with the expectation that he/she would have minimal 5 years of RTL design experience and 3 years of management experience in the multimedia, image processing or similar industry.




  • Lead ISP hardware IP development from spec. to tape out
  • Lead and mentor design team to solve all technical issues during project development
  • Guide and review design spec. and micro architecture with team members and keep the design and implementation in sync with overall architecture 
  • Establish project database management, methodology, design flow and guideline; enforce good engineering discipline and improve team's efficiency and effectiveness
  • Interface with other functional teams, such as algorithm, verification and firmware to resolve interdisciplinary issues and coordinate the task and schedule
  • Daily management of design team




  • BS-CS/BS-EE with at least 10 years' experience or MS with at least 8 years' experience in ASIC/SoC design
  • Strong multimedia/video/camera related system level knowledge and experience
  • In depth knowledge and experience of ASIC design flow is required, which include RTL coding (guideline, style, database management), simulation, FPGA verification, synthesis, timing closure, power estimation, power domain design, formal verification; successful tapeout and validation experience is a must
  • Experience of working with multi-site teams is preferred



  • Bachelor or Master, major in EE, CS or related area



  •  Shanghai, Pudong, Zhangjiang
  • #LI-NJ1

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers and will consider all applicants without regard to race, marital status, sex, age, color, religion, national origin, veteran status, disability or any other characteristic protected by law. EOE/MFDV

Requisition Number: 101446 
Country/Region/Location: China State/Province: Shanghai City: Shanghai 
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