PMTS Silicon Design Engineer

Location: Shanghai, Shanghai, CN

Company: Advanced Micro Devices

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What you do at AMD changes everything 


At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 


Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

 

PMTS Silicon Design Engineer – Feint

 

 

THE ROLE:

AMD IP FEINT team delivers industry leading high-performance interconnects IP for all AMD products including CPU, APU, dGPU. You'll be working with the global IP/SOC/PD/CAD team to deliver high quality netlists and constraints, support PD team to close P&R timing of tiles, and handles IP design quality check.

 

 

THE PERSON:

  • Strong analytical/problem solving skills and pronounced attention to details.
  • Must be a self-drive and able to independently drive tasks to completion.
  • Strong interpersonal and communication skills.
  • Strong responsibilities and team spirit.

 

 

 KEY RESPONSIBILITIES

  • Responsible for Front-End chip implementation including design, implementation and execution of the flow that starts with RTL code and ends with the delivery of a netlist package ready for physical design.
  • Responsible for ASIC design methodology and flow development, interfacing with EDA vendors on technology.
  • Responsible for cdc/lint, timing closure, lower power implementation and netlist quality check with RTL designer and PD team.
  • Technical lead for Front-End flow and Front-End chip implementation

 

 

 PREFERRED EXPERIENCE:

  • MS degree of EE,  10+ years working experience.
  • Familiar with Verilog RTL design/implementation and has experience of large digital ASIC project.
  • Familiar with front-end EDA tools and flows (Design compiler, PrimeTime, Conformal, VSI/VC-static, Formality, etc…)
  • Familiar with unix/linux and scripts (tcl, perl, etc.)
  • Familiar with physical design is a plus.
  • Strong background with Synthesis or physical implement experience.
  • Strong capability for problem-solving,  especially for critical timing issue and Front-end flow issue.
  • Familiar with lower power design methodology.
  • Good English skills on talking, presentation and writing documents. 
  • Good communication and strong sense of responsibility, task scheduling, and time management.

 

ACADEMIC CREDENTIALS:

  • Bachelor, Master's degree in Electrical or Computer engineering.

 

 

LOCATION:

  • Shanghai

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Requisition Number: 161524 
Country/Region/Location: China State/Province: Shanghai City: Shanghai 
Job Function: 
Design  

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