CIT Design Engineer

Location: Shanghai, Shanghai, CN

Company: Advanced Micro Devices

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What you do at AMD changes everything 


At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 


Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

 

THE ROLE:

CIT (Chiplet Interconnect Technology) team delivers industry leading high-performance interconnects IP for all AMD products including dGPU, APU, Server and Game consoles. CIT includes AMD Internal links for on-chip connections.

We are searching for a designer to join the fast-growing CIT team, and be responsible for defining, specifying, and implementing current and future high-speed I/O IPs. The candidate will be involved in digital design and will be to work on the micro-architecture of lead IPs.

THE PERSON:

People who have the passion to work on leading edge technology, who have solid design capability and communication skills will be successful in this role.

  • Strong team spirit
  • Desire to grow and learn
  • Drive to completion
  • Fluent verbal English

KEY RESPONSIBILITIES:

  • Defining and implementing the RTL of a new AMD chiplet interconnect IP
  • Participate in RTL implementation for functional blocks of the IP
  • Optimize RTL implementation from implementation perspective in cooperation with RTL and Architecture teams
  • Optimization of physical implementation in cooperation with Physical Design team.
  • Synthesis, Equivalence Checking, Clock-Domain Crossing (CDC) Analysis, Area/Power optimizations, Linting, Static Timing Analysis (STA)

 

PREFERRED EXPERIENCE:

  • Experience in digital front-end  implementation, including micro-arch. definition
  • Experience with state-of-the-art industry standard digital tools
  • RTL design experience with multi-clock, high frequency designs
  • Knowledge in digital RTL Design and Implementation
  • Basic understanding in high-speed I/O protocols (PCIe, USB, SATA, ethernet…)
  • Preferred experience in design with multiple clock domains

 

ACADEMIC CREDENTIALS:

  • Candidate is preferred to be MSEE with 3~9 years, or BSEE with minimum of 5-years’ experience in digital ASIC design.

 

LOCATION:

Shanghai

 

#L1-JW1



Requisition Number: 99643 
Country/Region/Location: China State/Province: Shanghai City: Shanghai 
Job Function: 
Design  

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