SMTS Silicon Design Engineer

Location: Shanghai, Shanghai, CN

Company: Advanced Micro Devices

Apply now

Apply for Job


What you do at AMD changes everything 


At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 


Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

 

SMTS Silicon Design Engineer (Verification for GCP)

 

THE ROLE:

AMD GCP team is a global GFX IP verification team and responsible to deliver high verification quality GFX IP for all AMD Graphic products. You will work with the global GCP teams on Graphic level verification and mainly focus on functional verification, partial on performance and HWEMU side. Besides RTL verification flow execution, you may also need to develop a UVM/C++ mixed GFX IP testbench and the whole verification environment build and validation. 

 

THE PERSON:

Familiar with RTL verification flow, has basic RTL design knowledge. Strong debug and problem-solving skills. Has good communication skills and good at teamwork. Be able to work both independently and coordinate with internal and external teams.

 

KEY RESPONSIBILITIES:

  • Work as a GFX IP verification engineer.
  • Work closely with Architecture and Design teams to understand relevant features the basic design.
  • Write Verification plan including test plan and responsible for verification quality.
  • Debugging RTL, ENV and Test bugs and improve regression passrate based on schedule request
  • Create and collect cover-points to drive functional coverage closure.
  • UVM/C++ Testbench development and maintenance.

 

PREFERRED EXPERIENCE:

  • Good at SystemVerilog, C/C++ language and UVM methodology
  • Good at Makefile and script, at least one, e.g. Shell, TCL, Perl or python
  • Experience/Background on CPU/GPU is a plus
  • Experience with Verilog/SystemVerilog design is a plus
  • Strong communication skill and teamwork is desired
  • Strong problem-solving skill is desired
  • Passion to work efficient and improve the current methodology
  • Good at written and spoken English

 

ACADEMIC CREDENTIALS:

  • Master is preferred, or Bachelor major in EE, CS, or neighboring area.

 

LOCATION:

Shanghai, Pudong, Zhangjiang

 

#LI-JG2



Requisition Number: 106508 
Country/Region/Location: China State/Province: Shanghai City: Shanghai 
Job Function: 
Design  

Apply now

Apply for Job

Share this Job