SMTS Silicon Design Engineer

Location: Shanghai, Shanghai, CN

Company: Advanced Micro Devices

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What you do at AMD changes everything 


At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 


Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

 

THE ROLE:

AMD NBIO (North Bridge IO) team delivers industry leading high-performance interconnects IP for all AMD products including dGPU, APU, Server and Game consoles.  NBIO global operates seamless from China, North America and Europe.

IOHUB sits in the center of all data paths, it includes 2 sub IP name as IOHub Core and IOMMU.   The IOMMU (I/O Memory Management Unit) is a system function that translates addresses used in DMA transactions, protects memory from illegal access by I/O devices, and remaps peripheral interrupts. It plays a critical role on IO virtualization technology which is widely used in today’s mega-data center.  Shanghai IOHUB team is expanding and hiring a verification lead focus on IOMMU sub IP.

 

As a global team, IOMMU DV lead has opportunities to travel to Canada, Serbia or America to attend some technique conferences, face to face to talk with global technique leads. It’s also a great chance to learn the word’s most advanced technique.

 

 

THE PERSON:

Candidate will work as local IOMMU verification leader,  lead a group of 4 engineers ( and growing ) and work with global IOHUB team on cutting edge IOMMU development. Candidate need to have solid IP verification background and outstanding global communication skill.

 

Someone who has DV lead experience with good Chinese and English communication skills should be basic qualified our requirement. There is also short travel to North America and night meeting possibility as the DV lead. 

 

KEY RESPONSIBILITIES:

  • IOMMU new feature effort scoping
  • IOMMU feature test plan and DRVR writer, split down the tasks and assign to engineers
  • Attend global conference call for verification strategy alignment, status sync up etc. with global team
  • Drive and monitor other engineers to accomplish tasks on schedule
  • Sign-off owned features/projects
  • Ramp-up new hires
  • Short term global travel if needed

 

PREFERRED EXPERIENCE:

  • Global company working experience,  fluent oral English
  • Complex IP/ASIC/SOC Design Verification, direct experience in IP/SOC or Processor (CPU or GPU) or Industry bus standard (PCI-e, HT) is preferred.
  • Good knowledge of UVM/Verilog/System C/SystemVerilog.
  • Solid background with hardware verification methodologies such as coverage-based verification methodology with the use of hardware assertions (PSL or SVA), insights into random techniques.
  • Experience of verification lead is an asset.
  • Experience of verification planning is an asset.
  • Knowledge of Virtualization is an asset.
  • Strong scripting languages (Perl, C Shell, Makefile, …) experience.
  • Strong collaboration skill set

 

ACADEMIC CREDENTIALS:

  • MSEE within 5-10 years, or BSEE within 8-12 years’ experience in digital ASIC/SOC design verification.

 

#L1-JW1



Requisition Number: 117047 
Country/Region/Location: China State/Province: Shanghai City: Shanghai 
Job Function: 
Design  

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