Verification Engineer of NBIO MPME

Location: Shanghai, Shanghai, CN

Company: Advanced Micro Devices

Apply now

Apply for Job


What you do at AMD changes everything 


At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 


Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

 

 

Verification Engineer of NBIO MPME 

THE ROLE:

 

 AMD NBIO (North Bridge IO) team delivers industry leading high-performance interconnects IP subsystems for all AMD products including Gaming APU and GPU, Client Desktop and Laptop APU, Server CPU and GPU etc. IP subsystems delivered by global NBIO organization includes PCIe, IOHUB (for high speed IO device routing and IO virtualization), CIT (for high speed interconnect among chiplets), DACC (for IO acceleration) and future opportunities. Global NBIO organization operates seamless from China, North America and Europe.

 

NBIO multi-subsystem interoperability, performance and emulation (MPME) team focus on interoperability verification, performance & power verification across subsystems, delivers performance architect models and emulation solutions for NBIO subsystems.

 

THE PERSON:

The successful candidate for this role will be an integral part of MPME team and mainly focus on NLP verification.  We are seeking a forward thinker to improve development process and drive innovation.

 

 

KEY RESPONSIBILITIES:

 

  • Work with global team on NLP verification strategy setup
  • Provide the technical leadership to the DV team for the power group DV tasks
  • Be involved technically in the porting/creation of the DV environment for the new design, test plan creation and implementation, coverage analysis, and regression cleanup
  • Forward thinker to improve development process and drive innovation
  • Collaborate with global engineering team on implementation of multiple programs
  • Provide technical guidance to junior engineers

 

 

PREFERRED EXPERIENCE:

 

  • Solid knowledge on SystemVerilog, UVM, C/C++, Verilog
  • Solid background with hardware verification methodologies such as coverage-based verification methodology with the use of hardware assertions (PSL or SVA)
  • Solid knowledge on scripting language like Perl, python, ruby
  • Hands on experiences on NLP and be familiar with UPF
  • Knowledge on PCIE is a big plus
  • Fluent verbal English for technical discussion with global team

 

ACADEMIC CREDENTIALS:

Candidate is preferred to be MSEE with minimum of 6 years, or BSEE with minimum of 8-year experience in digital ASIC/SOC design verification.

 

LOCATION:

Shanghai

 

#L1-JW1



Requisition Number: 148004 
Country/Region/Location: China State/Province: Shanghai City: Shanghai 
Job Function: 
Design  

Apply now

Apply for Job

Share this Job