SMTS Silicon Design Engineer

Location: Shanghai, Shanghai, CN

Company: Advanced Micro Devices

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What you do at AMD changes everything 


At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 


Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

 

 

 

What you do at AMD changes everything

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, Immersive platforms, and the data center.

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

SMTS Silicon Design Engineer

 

THE ROLE:

PCIe Subsystem team delivers industry leading high-performance PCIe IP subsystem for all AMD products including dGPU, APU, Server and Game consoles. PCIe subsystem supports the latest industry PCIe standard . You'll be working with the global team Architects/Designers/DV on PCIe subsystem IP Verification.

 

THE PERSON:

People who have the passion to work on leading edge technology, who have good communication skills will be promising in this role.

 

KEY RESPONSIBILITIES:

  • Develop and update infrastructure and environment for IP level design verification.
  • Closely working with Design and Architecture team to develop new verification component
  • Responsible for PCIe SS IP new features verification plan and verification closure
  • Responsible for PCS+PHY(Cadence/SNPS/AMD…) new feature development and all legacy feature verification closure

 

PREFERRED EXPERIENCE:

  • Solid background with ASIC design verification flow and multiple ASIC tape out experience
  • Team leader experience and experienced on testbench architecture.
  • Solid knowledge on UVM, SystemVerilog and Verilog is a must
  • SoC system or sub-system work experience is a plus
  • Fluent written English for technical discussion among global team, vocal is a plus
  • Knowledge on High speed IO/PCIe or Serdes PHY is a big plus
  • Knowledge on PCIe PCS or PCIE PIPE interface is a big plus
  • Knowledge on SNPS PCIe VIP is a plus
  • Knowledge on C++ or script language like python, ruby,perl is a plus
  • Located in Shanghai

 

ACADEMIC CREDENTIALS:

  • Solid education background of 211, 985 or top 100 ranking oversea universities
  • MSEE with 8+ years, or BSEE with minimum of 10+ years’ experience

 

LOCATION:

Shanghai

 



Requisition Number: 166422 
Country/Region/Location: China State/Province: Shanghai City: Shanghai 
Job Function: 
Design  

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