Sr. Silicon Design Engineer

Location: Shanghai, Shanghai, CN

Company: Advanced Micro Devices

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What you do at AMD changes everything 


At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 


Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

 

Front-End Design Engineer

 

THE ROLE:

AMD IP FEINT team delivers industry leading high-performance interconnects IP for all AMD products including CPU, APU, dGPU, and Game consoles. You'll be working with the global IP/SOC/PD/CAD team to deliver high quality netlists and constraints, support PD team to close P&R timing of tiles, and handles IP design quality check.

 

THE PERSON:

  • Strong analytical/problem solving skills and pronounced attention to details.
  • Must be a self starter, and able to independently drive tasks to completion.
  • Strong interpersonal and communication skills.
  • Strong responsibilities and team spirit.

 

KEY RESPONSIBILITIES:

  • Responsible for industry leading IP Synthesis/Formal/STA.
  • Responsible for industry leading IP LINT/CDC/VSI.
  • Responsible for industry leading IP regularly regression.
  • Responsible for function ECO implementation and LEC/DRC check.
  • Work with global IP teams to guarantee IP delivery quality.
  • Work with multiple global SOC teams to implement Tile.
  • Work with multiple global SOC teams to accomplish successful tapeout for AMD Sever/Client/dGPU/SCBU products.
  • Work with front-end integration team and physical design team on timing closure.
  • Co-ordinating design and implementation activities.

 

PREFERRED EXPERIENCE:

  • Minimum 2 years of experience with Verilog a MUST.
  • Familiar with front-end design flow.
  • Experience on synthesis, timing analysis and formal verification.
  • Excellent knowledge of verilog and a scripting language; experience with Perl and TCL is a plus.
  • Low power experience is a plus.
  • High speed design experience is a plus.
  • Industry Serdes design experience is a plus.

 

ACADEMIC CREDENTIALS:

  • Bachelor, Master's degree in Electrical or Computer engineering.

 

LOCATION:

Shanghai

 

#L1-JW1



Requisition Number: 95081 
Country/Region/Location: China State/Province: Shanghai City: Shanghai 
Job Function: 
Design  

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