78711_PCIE IP DV Engineer

Location: Shanghai, Shanghai, CN

Company: Advanced Micro Devices

Apply now

Apply for Job


What you do at AMD changes everything 


At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 


Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

 

<span style="font-family:"Calibri Light",sans-serif">PCIE IP <span style="font-family:"Calibri Light",sans-serif">Verification Engineer

 

<span style="font-family:"Calibri Light",sans-serif">THE ROLE:

<span style="font-family:"Calibri Light",sans-serif">AMD NBIO (North Bridge IO) team delivers industry leading high-performance interconnects IP for all AMD products including dGPU, APU, Server and Game consoles.  NBIO global operates seamless from China, North America and Europe.

<span style="font-family:"Calibri Light",sans-serif">PCIe IP is one of the most important IP in all AMD’s projects. Shanghai PCIe team contributed a lot on the first PCIe Gen4 product and are working on Gen5 product. So, this role provides a great opportunity for working on the most advanced PCIe technology.

<span style="font-family:"Calibri Light",sans-serif">As a global team, the candidate also has opportunities to travel to Canada, Serbia or America to attend some technique conferences, face to face to talk with global technique leads.

 

<span style="font-family:"Calibri Light",sans-serif">THE PERSON:

<span style="font-family:"Calibri Light",sans-serif">Good communicate skill, co-work spirit, strong self-learning and adaptability are preferring.

 

<span style="font-family:"Calibri Light",sans-serif">KEY RESPONSIBILITIES:

  • <span style="font-family:"Calibri Light",sans-serif">PCIe controller verification
  • <span style="font-family:"Calibri Light",sans-serif">Work with architecture/IP designers to get a full deep insight on the design under test
  • <span style="font-family:"Calibri Light",sans-serif">PCIe IP test bench build, verification component build

 

<span style="font-family:"Calibri Light",sans-serif">PREFERRED EXPERIENCE:

  • <span style="font-family:"Calibri Light",sans-serif">Complex IP Design Verification, direct experience in IP/SOC or Processor (CPU or GPU) or Industry bus standard (PCI-e, HT) is preferred.
  • <span style="font-family:"Calibri Light",sans-serif">Good knowledge of at least one verification methodology. UVM is preferred
  • <span style="font-family:"Calibri Light",sans-serif">Good knowledge of Verilog/C/C++/System C/SystemVerilog.
  • <span style="font-family:"Calibri Light",sans-serif">Verification insights into random techniques.
  • <span style="font-family:"Calibri Light",sans-serif">Experience of verification lead is an asset.
  • <span style="font-family:"Calibri Light",sans-serif">Experience of PCIe verification is an asset.
  • <span style="font-family:"Calibri Light",sans-serif">Experience in power verification is an asset.
  • <span style="font-family:"Calibri Light",sans-serif">Verification of Virtualization is an asset.
  • <span style="font-family:"Calibri Light",sans-serif">Good at both Oral English and written English

 

<span style="font-family:"Calibri Light",sans-serif">ACADEMIC CREDENTIALS:

<span style="font-family:"Calibri Light",sans-serif">MSEE within 2-5 years, or BSEE within 4-7 years’ experience in digital ASIC/SOC design verification

 

<span style="font-family:"Calibri Light",sans-serif">LOCATION:

<span style="font-family:"Calibri Light",sans-serif">Shanghai

 

<span style="font-family:"Calibri Light",sans-serif">APPLY:

<span style="font-family:"Calibri Light",sans-serif">Email to <span style="font-family:"Calibri Light",sans-serif">bella.yu@amd.com


<span style="font-family:"Calibri Light",sans-serif">AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers and will consider all applicants without regard to race, marital status, sex, age, color, religion, national origin, veteran status, disability or any other characteristic protected by law. EOE/MFDV

<span style="font-family:"Calibri Light",sans-serif">#LI-BY1



Requisition Number: 78711 
Country: China State: Shanghai City: Shanghai 
Job Function: 
Design  

Apply now

Apply for Job

Share this Job