USB IP Design Engineer

Location: Shanghai, Shanghai, CN

Company: Advanced Micro Devices

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What you do at AMD changes everything 


At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 


Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

 

MTS IP Designer

 

THE ROLE:

It is a must that the candidate has one or more of the following experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, USB(3.0/2.0/1.1; HSIC/host/device/OTG) system, NAND Flash host controller/BCH/double-data-rate interface, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet, JTAG, etc.

 

THE PERSON:

The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, specialized knowledge plus broad technical knowledge that facilitates integrative thinking, driving execution of quality and timely result, capability  to solve complex, novel and no-recurring problems and decision-making on critical technical areas

 

KEY RESPONSIBILITIES:

  • Work with team members and apply his/her design techniques to work on different phases of complex logic design for ASIC/SOC projec
  • technical leading on the following tasks from time to time: specification, top level SOC design tasks, HDL coding, etc

PREFERRED EXPERIENCE:

  • Master in Electrical Engineering, Computer Science or related
  • Deep understanding on ASIC design verification flow
  • RTL coding with Verilog/System Verilog

 

ACADEMIC CREDENTIALS:

MSEE with minimum of 6 years, or BSEE with minimum of 8 years experiences in digital ASIC/SOC design verification

 

LOCATION:

Shanghai/BeiJing

#LI-BY1



Requisition Number: 76617 
Country: China State: Shanghai City: Shanghai 
Job Function: Design

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