Packaging Engineer (MTS)

Location: Singapore, Singapore, SG

Company: Advanced Micro Devices

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What you do at AMD changes everything 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.


Packaging Engineer


The Role:

We are offering an exciting and unique position for anyone that has silicon design expertise coupled with Die + Substrate interaction level expertise to help us usher in and develop the next generation/future of advanced 3D IC packaging technology.


The Person:

The candidate is an experienced Silicon Physical Layout or Package Layout Engineer that has excellent communication & project management skills and can complete the design task with minimal supervision. They should be able to work on a fast phase environment and collaborate well with others. A proactive, outstanding teammate who focuses on teamwork, team building, and growing team success.

AMD's environment is fast paced, results oriented and built upon a legion of forward-thinking people with a passion for winning technology!


Key Responsibilities:

  • Codesign with SOC team to complete Bump matrix and Interposer design for 2.5D, COWOS, INFO and other advanced packaging technologies (Chiplet).
  • Codesign with Signal/Power Integrity and PCB design team to complete a substrate layout that will meet the design objectives for performance, cost and quality.
  • Support substrate design for probe card substrate, test chips and test vehicles for technology development.
  • Contribute to the development and enhancements of process and methodologies to improve design efficiency.
  • Interact with Assembly houses and substrate vendors to achieve cost-efficient and high-quality design.
  • Mentor Junior Colleagues to enhance layout practices.


Preferred Experience:

  • Experienced on designing Silicon Interposers or complex substrate design.
  • Very good understanding of Signal Integrity and power integrity principles.
  • Knowledge on using CAD Layout tools such as Cadence SIP, APD 17.4, First Encounter, ICC2 or other Packaging or Silicon Physical Layout Software.
  • Knowledge on Perl or Skill Script Programming are a plus.
  • Experience dealing with assembly, foundry, and substrate vendors.


Academic credentials:

  • B.A. Sc. in Electrical Engineering, Computer Engineering, or Engineering Science






AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers and will consider all applicants without regard to race, marital status, sex, age, color, religion, national origin, veteran status, disability or any other characteristic protected by law. EOE/MFDV

Requisition Number: 102723 
Country/Region/Location: Singapore State/Province: Singapore City: Singapore 
Job Function: 
Packaging Engineering  

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