MTS Silicon Design Verification Engineer

Location: Singapore, Singapore, SG

Company: Advanced Micro Devices

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What you do at AMD changes everything 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.


MTS Silicon Design Verification Engineer



This role is for AMD’s next generation state of art high speed IOs (PHYs) verification at Singapore office. You will be interacting with a team of smart analog and digital designers and verification engineers, building complex testbenches analog/digital/FW IPs and make sure that design is bug free. 



We are looking for a logic designer for a mixed signal group developing differentiating IP for AMD's processor and graphic products. You will have knowledge of UVM, SystemVerilog, debugging skills.  You will naturally have a lot of drive and have great sense of ownership. We are looking for a great teammate with excellent communication skills.



  • We are looking for expert verification engineers for our next generation of high-speed IO verification.
  • Once candidate is on board, he/she will ramp on with our various protocols about high speed, will work closely with assigned mentor to ramp up on various part of our verification.
  • You will be owing a full block in next six months. Candidate will also learn about analog verification and firmware verification.
  • We are looking for this brilliant teammate who is committed to meeting deadlines and an aptitude to thrive in a fast-paced multi-tasking environment.
  • Effective communication across organizations/levels is also key for program status update (both working details to the team, and executive summary for Executive communication).
  • Be it developing new programs to support the strategic direction of the organization or implementing and managing changes/ interventions, you will work towards projects goals being achieved.



  • Focus on Logic Design, Computer Architecture and 9 years of industry experience in Design Verification.
  • Hands-on experience in UVM, System Verilog logic, Verilog design and verification
  • Hands-on experience in Formal Verification and related tools
  • Hands-on experience with low power design and power analysis flows
  • Familiar with languages like Perl, C/C++ etc
  • Communicate technical details with team members both on-site and remotely
  • Conduct design reviews of designs in technical presentations to peers and management
  • Strong candidates may also have SERDES (PCIe, SATA, USB) experience, high level understanding of analog and mixed signal circuits, and experience with mixed signal simulators.
  • Experience in managing horizontally across multiple internal functional organization.
  • Strong interpersonal communication, analytical, project management, task & time management, and excellent executive communication skills.
  • Minimum of six years of experience for MTS role is ideal



  • BS in electrical/electronic/computer-science or related field is required.




AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers and will consider all applicants without regard to race, marital status, sex, age, color, religion, national origin, veteran status, disability or any other characteristic protected by law. EOE/MFDV





Requisition Number: 160602 
Country/Region/Location: Singapore State/Province: Singapore City: Singapore 
Job Function: 

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