Senior DFT Engineer

Location: Singapore, Singapore, SG

Company: Advanced Micro Devices

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What you do at AMD changes everything 


At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 


Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

 

Senior DFT Engineer

 

THE ROLE:

  • Pre-silicon verification of DFT schemes and patterns using Industry standard tools.
  • Diagnose and debug the pattern failures on ATE to root cause the problem
  • Responsible for implementing techniques to Optimize Test Time, Dynamic IR drop in scan shift and Yield improvement
  • Work closely with Design Team and Product Engineering Teams to quickly resolve issues and meet high volume production schedule

 

 

THE PERSON:

AMD is looking for a Senior DFT Engineer to join an exciting position in Product Verification Team. The candidate will be working on Scan, MBIST and iJTAG manufacturing test pattern development for Versal architecture based Adaptive Compute Accelerated Platform (ACAP) products. These are complex SoC designs having ARM based Processor to critical IPs which provide automotive, data centre, machine learning and high-speed communication solutions. You will work closely with designers to make sure DFT structures are correctly inserted, with test engineers to test scan/mbist production patterns across PVT conditions, and with yield engineers to debug and root-cause defects. You will be implementing test solutions using FPGA logic to apply Test patterns and optimize Test time.  The role includes learning and usage of Firmware application in Test Patterns.

 

 

KEY RESPONSIBILITIES:

  • Develop Structural Test Patterns (Scan/MBIST/iJTAG) for multiple IPs in Next Generation Xilinx MPSoCs
  • Achieve Structural test coverage target of the Digital logic, SRAMs and Mixed-Signal IPs using ATPG and different fault models
  • Develop iJTAG Network and Memory BIST / Repair patterns
  • Design FPGA Logic using Xilinx vivado software to apply test patterns and enhance the diagnostic capability

 

PREFERRED EXPERIENCE:

  • 2-5 years’ experience in DFT and ATPG
  • Knowledge of Fault modelling, Scan architecture, Scan compression and Memory testing techniques
  • Expertise with industry Standard tools like TestKompress, DFT advisor, DFT Compiler, VCS
  • Experience in Gate Level Simulation and Debug
  • Good understanding of Digital Design and ASIC design flow
  • Knowledge in VHDL/Verilog and IEEE 1149.1 standard
  • Knowledge of Perl / Shell Scripting and C++ is a plus
  • Knowledge of FPGA and Vivado Software is a plus
  • Self-motivated and a strong team-player
  • Strong analytical and problem-solving skills
  • Ability to learn new tools and technologies

 

 

ACADEMIC CREDENTIALS:

  • Bachelor/Master’s degree in Electrical/Electronic/Computer Engineering

 

LOCATION:

Singapore


AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers and will consider all applicants without regard to race, marital status, sex, age, color, religion, national origin, veteran status, disability or any other characteristic protected by law. EOE/MFDV

 

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Requisition Number: 168408 
Country/Region/Location: Singapore State/Province: Singapore City: Singapore 
Job Function: 
Reliability & Test  

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